1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly, to an Electrically Erasable PROM (E.sup.2 PROM) and a method for fabricating the same.
2. Description of the Related Art
An E.sup.2 PROM includes a semiconductor chip on which a memory section having a plurality of memory cell transistors and a peripheral circuit section are formed. In the E.sup.2 PROM, non-volatile transistors are used as the memory cell transistors.
FIGS. 3 and 4 show a cross-sectional structure of a typical memory cell transistor used in the E.sup.2 PROM. The memory cell transistor includes a P-type silicon substrate 51, on which a gate oxide 52, a floating gate 53, an ONO film 54, and a control gate 55 are formed in this order, as shown in FIG. 3. The ONO film 54 is formed of three layers (i.e., two SiO.sub.2 films and an SiN film interposed therebetween). The ONO film 54 electrically insulates the floating gate 53 from the control gate 55. The floating gate 53 is surrounded by an insulating film and in an electrically floating state. However, the floating gate 53 is capacitively coupled with the control gate 55, and the electrical potential of the floating gate 53 is controlled by the control gate 55. A source 56 and a drain 57 are formed of N-type diffusion layers in the P-type silicon substrate 51.
In the E.sup.2 PROM, electric carriers stored in the floating gate 53 can be released to the outside by applying a relatively high voltage between the control gate 55 and the source region 56. In this area, the E.sup.2 PROM can be more easily handled than an EPROM in which the UV-ray irradiation is used for releasing the electric carriers.
Erasing methods of data in the E.sup.2 PROM include a positive bias erasing method and a negative bias erasing method. According to the positive bias erasing method, as shown in FIG. 3, a gate 58 is set at 0 volts; a positive high bias voltage (such as 12 volts) is applied to the source region 56; and the drain region 57 is set at Floating. In this method, a breakdown is avoided between the source region 56 and the substrate 51, so that the source region 56 is formed of a double diffusion structure having a diffusion region of a low concentration. However, a longer gate length is required, resulting in some difficulty in reducing the size of the memory cell.
According to the negative bias erasing method, as shown in FIG. 4, a negative bias (such as -12 volts) is applied to the gate 58; the source region 56 is set at 5 volts; and the drain region 57 is set at Floating. In this method, the source region 56 can be low-biased (such as 5 volts), so that no breakdown occurs between the source region 56 and the substrate 51. Accordingly, it is not necessary to form the source region 56 in the double diffusion structure, thereby shortening the gate length. Thus, the negative bias erasing method has been proposed for reducing the size of a memory cell of the E.sup.2 PROM.
In an E.sup.2 PROM, the peripheral circuit section has a CMOS (Complementary MOS) in order to lower the consumption of power. FIGS. 5A and 5B show structures of the CMOS in which a P-type single crystalline silicon is used as the substrate 51. In this CMOS, as shown in FIG. 5A, MOS transistors of an N-channel type and a P-channel type are isolated by a field oxide 90. In the case of employing the P-type silicon substrate 51, an N-channel transistor 71 in the peripheral circuit section has a source (N.sup.+ -type source) region 76 and a drain (N.sup.+ -type drain) region 77 which are formed as the N-type diffusion layers in a P-type region 72 (hereinafter, referred to as a P-type well), the source region 76 and the drain region 77 being formed in the P-type substrate 51 in the vicinity of the surface thereof. An insulating layer 79 made of a silicon oxide is formed on the surface of the substrate 51, overlapping ends of the source 76 and the drain 77. A gate 78 is formed on such an insulating layer 79.
In a P-channel transistor 81 of the peripheral circuit, an N-type region 83 of a relatively low concentration (hereinafter, referred to an N-type well) is formed in the substrate 51 in the vicinity of the surface thereof, since the substrate 51 is of the P type. The N-type well 83 includes a source (P.sup.+ -type source) region 86 and a drain (P.sup.+ -type drain) region 87 of the P-type diffusion layer.
An insulating layer 89 made of an oxide film is formed on the surface of the substrate 51, overlapping both ends of the source 86 and the drain 87. A gate 88 is formed on such an insulating layer 89.
When the negative bias erasing method is performed in the E.sup.2 PROM having such a CMOS peripheral circuit section, as shown in FIG. 5B, a negative bias should be applied to the N-channel transistor 71 of the peripheral circuit section, in order to remove electrons from the floating gate 53 of the memory cell transistor. In this case, however, PN junctions between the source/drain of the N-channel transistor of the peripheral circuit section and the substrate receive a forward bias, so that a larger current flows through the PN junctions. Thus, the above method cannot work. Accordingly, the P-type substrate 51 and the P-type well 72 should be electrically separated from each other when the negative bias is applied to the P-type well 73 of the peripheral circuit. As a result, as shown in FIG. 5C, the P-type well 72 should be surrounded by a deep N-type well 73.
In order to surround the P-type well 72 with the deep N-type well 73, a large area for double well structure is required, resulting in an increase of the chip size. Thus, an advantage in that the negative bias erasing method reduces the chip size cannot be attained.